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 DATASHEET
PRECISION AUDIO CLOCK SOURCE Description
The ICS661 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal. The device uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. Please contact IDT if you have a requirement for an input and output frequency not included here - we can rapidly modify this product to meet special requirements.
ICS661 Features
* * * * * * * *
Packaged in 16-pin TSSOP Available in Pb (lead) fere package Clock or crystal input Low phase noise Low jitter Exact (0 ppm) multiplication ratios Reference clock output available Support for 256, 384, 512, and 768 times sampling rate
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDDR
X2 Crystal Oscillator
REF
X1/REFIN
SELIN S3:0 PLL Clock Synthesis
4
CLK
GND (P13)
GND (P6)
GND (P5)
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Pin Assignment
X1/REFIN VDD VDD S0 GND GND S3 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 REF VDDR GND SELIN VDDO S1 CLK
Output Clock Selection Table
S3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input Frequency (MHz)
27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
Output Frequency (MHz)
8.192 11.2896 12.288 24.576 12.288 16.9344 18.432 36.864 16.384 22.5792 24.576 49.152 24.576 33.8688 36.864 73.728
16-pin 4.40 mil body, 0.50 mm pitch TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1/REFIN VDD VDD S0 GND GND S3 S2 CLK S1 VDDO SELIN GND VDDR REF X2
Pin Type
Input Power Power Input Power Power Input Input Output Input Power Input Power Power Output Input Power supply for crystal oscillator. Power supply for PLL.
Pin Description
Connect this pin to a crystal or clock input
Output frequency selection. Determines output frequency per table above. On chip pull-up. Connect to ground. Ground for output stage. Output frequency selection. Determines output frequency per table above. On chip pull-up. Output frequency selection. Determines output frequency per table above. On chip pull-up. Clock output. Output frequency selection. Determines output frequency per table above. On chip pull-up. Power supply for output stage. Low for clock input, high for crystal. On chip pull-up. Connect to ground. Power supply for reference output. Ground to turn off REF. Reference clock output. Connect this pin to a crystal. Leave open if using a clock input.
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Application Information
Series Termination Resistor
Clock output traces should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 . capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high performance mixed-signal IC, the ICS661 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS661 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI and obtain the best signal integrity, the 33 series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS661. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Recommended Power Supply Connection for Optimal Device Performance
V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead V D D P in
B ulk D ecoupling C apacitor (such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
All power supply pins must be connected to the same voltage, except VDDR and VDDO may be connected to a lower voltage in order to change the output level. If the reference output is not used, ground VDDR.
Crystal Load Capacitors
If a crystal is used, the device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS661. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 5.5 V
Rating
-0.5 V to VDD+0.5 V -40 to +85 C -65 to +150 C 125 C 260 C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-40 +3.0
Typ.
Max.
+85 +3.6
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85 C
Parameter
Operating Voltage
Symbol
VDD VDDO VDDR
Conditions
Min.
3.0 1.8 1.8 2
Typ.
Max.
3.6 VDD VDD 0.8
Units
V V V V V V V
Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Supply Current Short Circuit Current Nominal Output Impedance Input Capacitance Internal Pull-up Resistor
VIH VIL VOH VOH VOL IDD IOS ZOUT Input pins IOH = -4 mA IOH = -20 mA IOL = 20 mA No Load Each output
VDD-0.4 2.4 0.4 25 65 20 7 120
V mA mA pF k
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85 C
Parameter
Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Duty Cycle Jitter, Short term Jitter, Short term Jitter, Long term Jitter, Long term Single Sideband Phase Noise Single Sideband Phase Noise Actual Mean Frequency Error versus Target
Symbol
tOR tOF tOD
Conditions
20% to 80%, 15 pF load 80% to 20%, 15 pF load At VDD/2, 15 pF load Reference clock off Reference clock on Reference clock off; 10 us delay Reference clock on; 10 us delay Reference clock off; 10 kHz offset Reference clock on; 10 kHz offset
Min.
Typ.
27
Max.
28 1.5 1.5
Units
MHz ns ns % ps p-p ps p-p ps p-p ps p-p dBc dBc ppm
45
49 to 51 175 175 300 300 -110 -110 0
55
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
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Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
16
Millimeters Symbol
E1 INDEX AREA E
Inches Min Max
Min
Max
12 D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A2 A1
A
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
ICS661GI ICS661GIT ICS661GILF ICS661GILFT
Marking
ICS661GI ICS661GI 661GILF 661GILF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
-40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc. www.idt.com
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA


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